In the field of multiprocessor communications, two problems have usually arisen. First, there is the problem of interprocessor communication. Secondly, there is the problem of synchronization of operations among the processors so that each processor operates on an up-to-date and coherent set of input data.
One prior art solution, having high bandwidth communication, is a crossbar switch, directly connecting each processor's local memory with that of every other processor. This is known as a "fully connected" multiprocessor. However, the cost of a full crossbar switch grows as the square of the number of processors. Thus, it is not often implemented in practice.
Other prior art solutions are found by reference to U.S. Pat. Nos. 4,096,566; 4,443,861; 4,494,192; 4,574,345; 4,688,171; 4,814,984; 4,847,756; 4,862,350; 4,872,125; 4,873,656; 4,907,146; 4,910,705; 4,912,633; 4,918,589; 4,918,596; 4,930,069; 4,935,866; and 4,459,655.
In some applications, for example, in multichannel digital signal processing, prior art techniques have made use of simplified versions of the general multiprocessor communication and synchronization problems. When input signals are sampled in time at a fixed rate of 1/T.sub.s, operations can often be preformed repetitively as each new input data vector is ready, rather than in a longer or less-structured sequence. Communication among multiprocessors (or input/output units or storage units) can sometimes be limited to a modest number of streams of data which appear and are consumed at the same fixed sampling rate 1/T.sub.s. These streams flow between certain modules in a pattern Which is known in advance. Thus, a fully-connected multiprocessor system is not necessary.
In such an application, a common communication bus having a cycle time of T.sub.b .ltoreq.T.sub.s /N can be time multiplexed, where N is the total number of time slots. Each separate stream of data is assigned a time slot T.sub.b seconds within a fixed sequence of N slots.ltoreq.T.sub.s seconds long. This prior art technique is often referred to as time-domain-multiplexing (TDM). In prior art TDM communication, the communication bus or channel carries data only, because the order of time slots has been prearranged.
The efficiency of TDM involves a limitation: the connectivity of the data flow must be changed by reassigning time slots using a mechanism separate and apart from the TDM channel itself, e.g., changing a ROM or a logic decoder in each processor or module, or reprogramming the processors via other channels.
Furthermore, the ratio of sampling interval to channel cycling time is the upper limit on the number of slots available. This limits the number of different streams of data that can be communicated.
A further difficulty with TDM as a means of interprocessor communication is the existence of simultaneous multiple rates of operation. For example, decimation algorithms produce results at multiples of T.sub.s. Block-oriented algorithms, such as Fast Fourier Transforms, demand and produce data in block intervals long compared to T.sub.s. Finally, human-controlled parameters may change slowly compared to these or other signals, with potentially many such human-controlled parameters. In the prior art TDM channel communication, these different sampling rates have not been accommodated in a single communications channel.